Conventional microelectronic devices are packaged in a planar or two-dimensional (2D) surface-mount configuration. In this configuration, the package size (particularly the footprint) is dictated by both the number of and physical dimensions of the integrated circuit (IC) chips or other discrete devices included in the package, as well as the area occupied by the discrete surface-mounted passive components utilized. There is a continuing demand for smaller electronic products that at the same time provide a higher level of functionality. Hence, there is a concomitant demand for higher-performance, smaller-footprint packaged microelectronic devices for use in such products. In response, researchers continue to develop three-dimensional (3D) integration or chip-stacking technologies as an alternative to the conventional 2D format. By implementing 3D integration, multiple die may be “vertically” arranged (in the third dimension) in a single packaged electronic device, with adjacent die communicating by way of 3D (or “vertical”) metal interconnects extending through the thicknesses of the die substrates. 3D integration may be done at the wafer level (wafer-to-wafer bonding), the die level (die-to-die bonding), or in a hybrid format (die-to-wafer bonding). 3D packages can provide various advantages, such as shorter signal propagation delay (and thus faster signal processing), lower power consumption, reduced cross-talk, smaller package footprint, smaller device size, and higher input/output (I/O) count and density. Moreover, the different die stacked in the 3D package may be configured to provide different functions. For example, one die might include an active electronic device while another die might include an arrangement of passive components (resistors, capacitors, inductors, etc.), an array of memory modules, or a ground plane that communicates with several interconnects.
The formation of 3D metal interconnects has generally been accomplished by either a “vias first” approach or a “vias last” approach. In the “vias first” approach, the interconnects are formed prior to circuitry fabrication, substrate thinning, and substrate (die or wafer) bonding. In the “vias last” approach, the interconnects are formed after circuitry fabrication, substrate thinning, and substrate bonding. Particularly in the case of the “vias last” approach, the interconnect metal may need to be deposited through more than one layer of material in order for the metal to land on the surface of a contact pad and form a low-resistance electrical coupling with the contact pad. For example, to reach the contact pad the interconnect metal may need to be deposited through a deep via that extends through the entire thickness of one substrate and possibly partially into the thickness of an adjacent substrate where the contact pad is located, as well as through one or more intervening layers between these two substrates such as bonding layers, insulating layers, passivation layers, etc. Moreover, as a result of preceding material addition steps, an etching step (i.e., “bottom-clear” etching) such as deep reactive ion etching (DRIE) is typically required to expose the contact pad prior to the interconnect metallization step. Effective etching and interconnect metallization steps become more challenging as the aspect ratio (i.e., depth-to-diameter) of the vias increases.
There continues to be a need for improved methods for fabricating electronic devices that provide high-quality, low-resistance contact between interconnects and contact pads.